1. Field
Subject matter disclosed herein relates to cache coherence of a processor system that includes persistent memory.
2. Information
Computer systems may utilize a shared memory multiprocessor (SMP) configuration. Increasing the number of processors in such a computer system sharing a same main memory may enhance performance of the system. A computer system may incorporate coherency protocol to assure coherency between information read from cache memory and information read from main memory. For example, if one processor has updated information stored in main memory, the change in the information may be reflected in copies stored in memory caches of other processors.
Computer systems may use any of a number of coherency protocols, such as the MESI protocol, for example, to perform coherency management. The MESI protocol may manage cache lines in a cache memory by assuming that the cache lines are in one of four states, namely “M” (Modified), “E” (Exclusive), “S” (Shared), and “I” (Invalid) states. In a computer system using the MESI protocol, individual processors may determine whether to issue a cache coherency management request for a particular cache line based, at least in part, on its MESI state.